JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/05/2023
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Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. Constraining Incoming SYSREF Signal 5.2. Programmable RBD Offset 5.3. Programmable LMFC Offset 5.4. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

2.6. Channel Bonding

The JESD204B IP supports channel bonding—bonded (PMA bonding for Intel Agilex® 7, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX) and non-bonded modes.

The channel bonding mode that you select may contribute to the transmitter channel-to-channel skew. A bonded transmitter datapath clocking provides low channel-to-channel skew as compared to non-bonded channel configurations.

For Intel® Stratix® 10 L-tile and H-tile, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices, refer to PMA Bonding chapter of the respective Transceiver PHY User Guides , about how to connect the ATX PLL and fPLL in bonded configuration and non-bonded configuration. For the non-bonded configuration, refer to Implementing Multi-Channel xN Non-Bonded Configuration. For bonded configuration, refer to Implementing x6/xN Bonding Mode.

  • In PHY-only mode, you can generate up to 32 channels, provided that the channels are on the same side. In MAC and PHY integrated mode, you can generate up to 8 channels.
    Note: The maximum channels of 32 is for configuration simplicity. Refer to the Intel® FPGA Transceiver PHY User Guide for the actual number of channels supported.
  • In bonded channel configuration, the lower transceiver clock skew for all channels result in a lower channel-to-channel skew.
    • For Stratix V, Arria V, and Cyclone V devices, you must use contiguous channels when you select bonded mode. The JESD204B IP automatically selects between ×6, ×N or feedback compensation (fb_compensation) bonding depending on the number of transceiver channels you set.
    • For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 L-tile and H-tile devices, you do not have to place the channels in bonded group contiguously. Refer to Table 7 for the clock network selection. Refer to Channel Bonding section of the respective Transceiver PHY User Guides for more information about PMA Bonding.
    • For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, you must use contiguous channels to enable channel bonding with NRZ PMA transceiver channels.
  • In non-bonded channel configuration, the transceiver clock skew is higher and latency is unequal in the transmitter phase compensation FIFO for each channel. This may result in a higher channel-to-channel skew.
Table 6.   Maximum Number of Lanes (L) Supported in Bonded and Non-Bonded Mode
Device Family Core Variation Bonding Mode Configuration Maximum Number of Lanes (L)

Intel Agilex® 7

Intel® Stratix® 10

Intel® Arria® 10

Intel® Cyclone® 10 GX

Stratix V

Arria V GZ

Cyclone V

 PHY only Bonded 32 2
Non-bonded 32 2
MAC and PHY Bonded 8
Non-bonded 8
Arria V PHY only Bonded 32 2
Non-bonded 32 2
MAC and PHY Bonded 6
Non-bonded 8
Table 7.  Clock Network Selection for Bonded Mode
Note: The clock network selection is not applicable for Intel® Stratix® 10 E-tile devices.
Device Family L ≤ 6 L > 6

Intel® Stratix® 10 L-tile and H-tile

Intel® Arria® 10

Intel® Cyclone® 10 GX

×6 ×N 3
Stratix V ×6 Feedback compensation
Arria V ×N ×N
Arria V GZ ×6 Feedback compensation
Cyclone V ×N ×N
Related Information
2 The maximum lanes listed here is for configuration simplicity. Refer to the Intel® FPGA Transceiver PHY User Guides for the actual number of channels supported.
3 Bonded mode is not supported for data rate > 15 Gbps. Refer to the respective datasheet for the maximum data rate and channel span supported by the ×N clock network and the transceiver power supply operating condition for your device.
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