JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/05/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents RX CGS

The CGS phase is the link up phase that monitors the detection of /K28.5/ character.

The CGS phase is achieved through the following process:

  • Once the word boundary is aligned, the RX PHY layer detects the /K28.5/ 20-bit boundary and indicate that the character is valid.
  • The receiver deasserts SYNC_N on the next frame boundary (for Subclass 0) or on the next LMFC boundary (for Subclass 1 and 2) after the reception of four successive /K/ characters.
  • After correct reception of another four 8B/10B characters, the receiver assumes full code group synchronization. Error detected in this state machine is the code group error. Code group error always trigger link reinitialization through the assertion of SYNC_N signal and this cannot be disabled through the CSR. The CS state machine is defined as CS_INIT, CS_CHECK, and CS_DATA.
  • The minimum duration for a synchronization request on the SYNC_N is five frames plus nine octets.