JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/18/2022
Public
Document Table of Contents

6.2. JESD204B Parameters

The parameters in both the FPGA and ADC should be set to the same values. For example, when you set K = 32 on the FPGA, set the converter's K value to 32 as well. Scrambling does not affect the link initialization in the CGS and ILAS phases but in the user data phase. When scrambling is enabled on the ADC, the FPGA descrambling option has to be turned on using the "Enable scramble (SCR)" option in the JESD204B IP core Platform Designer parameter editor. When scrambling is enabled on the FPGA, the DAC descrambling has to be turned on too.

Check these items:

  • Turn off the scrambler and descrambler options as needed.
  • Use single lane configuration and K = 32 value to isolate multiple lane alignment issue.
  • Use Subclass 0 mode to isolate SYSREF related issues like setup or hold time and frequency of SYSREF pulse.

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