JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/18/2022
Public
Document Table of Contents

4.5. Reset Scheme

All resets in the JESD204B IP are synchronous reset signals and should be asserted and deasserted synchronously.
Note: Ensure that the resets are synchronized to the respective clocks for reset assertion and deassertion.
Table 24.   JESD204B IP Resets
Reset Signal Associated Clock Description

txlink_rst_n

rxlink_rst_n

TX/RX Link Clock Active low reset. Intel® recommends that you:
  • Assert the txlink_rst_n/rxlink_rst_n and txframe_rst_n /rxframe_rst_n signals when the transceiver is in reset.
  • Deassert the txlink_rst_n and txframe_rst_n signals after the Intel® FPGA PLL IP is locked and the tx_ready[] signal from the Transceiver Reset Controller is asserted.
  • Deassert the rxlink_rst_n and rxframe_rst_n signals after the Transceiver CDR rx_islockedtodata[] signal and rx_ready[] signal from the Transceiver Reset Controller are asserted.

The txlink_rst_n/rxlink_rst_n and txframe_rst_n /rxframe_rst_n signals can be deasserted at the same time. These resets can only be deasserted after you configure the CSR registers.

txframe_rst_n

rxframe_rst_n

TX/RX Frame Clock Active low reset controlled by the clock and reset unit. If the TX/RX link clock and the TX/RX frame clock has the same frequency, both can share the same reset.

tx_analogreset[L-1:0]

rx_analogreset[L-1:0]

Transceiver Native PHY Analog Reset Active high reset controlled by the transceiver reset controller. This signal resets the TX/RX PMA.
The link clock, frame clock, and AVS clock reset signals (txlink_rst_n/rxlink_rst_n, txframe_rst_n/rxframe_rst_n and jesd204_tx_avs_rst_n/jesd204_rx_avs_rst_n) can only be deasserted after the transceiver comes out of reset. 28
Note: This signal is not applicable for Intel® Agilex™ and Intel® Stratix® 10 E-tile devices.

tx_analogreset_stat[L-1:0]

rx_analogreset_stat[L-1:0]

Transceiver Native PHY Analog Reset TX PMA analog reset status port connected to the transceiver reset controller. 29
Note: This signal is applicable only for Intel® Stratix® 10 L-tile and H-tile devices.

tx_digitalreset[L-1:0]

rx_digitalreset[L-1:0]

Transceiver Native PHY Digital Reset Active high reset controlled by the transceiver reset controller. This signal resets the TX/RX PCS.
The link clock, frame clock, and AVS clock reset signals (txlink_rst_n/rxlink_rst_n, txframe_rst_n/rxframe_rst_n and jesd204_tx_avs_rst_n/jesd204_rx_avs_rst_n) can only be deasserted after the transceiver comes out of reset. 28
Note: This signal is not applicable for Intel® Agilex™ and Intel® Stratix® 10 E-tile devices.

tx_digitalreset_stat[L-1:0]

rx_digitalreset_stat[L-1:0]

Transceiver Native PHY Digital Reset TX PCS digital reset status port connected to the transceiver reset controller.29
Note: This signal is applicable only for Intel® Stratix® 10 L-tile and H-tile devices.

jesd204_tx_avs_rst_n

jesd204_rx_avs_rst_n

TX/RX AVS (CSR) Clock Active low reset controlled by the clock and reset unit. Typically, both signals can be deasserted after the core PLL and transceiver PLL are locked and out of reset. If you want to dynamically modify the LMF at run-time, you can program the CSRs after AVS reset is deasserted. This phase is referred to as the configuration phase.

After the configuration phase is complete, then only the txlink_rst_n/rxlink_rst_n and txframe_rst_n/rxframe_rst_n signals can be deasserted.

28 Refer to the respective Transceiver PHY IP User Guides for the timing diagram of the tx_analogreset, rx_analogreset, tx_digitalreset, and rx_digitalreset signals.
29 Refer to the Intel® Stratix® 10 L- and H-tile Transceiver PHY IP User Guide for the timing diagram of the tx_analogreset_stat, rx_analogreset_stat, tx_digitalreset_stat, and rx_digitalreset_stat signals.

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