JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

4.3.1.2. Subclass 1 Operating Mode

The JESD204B IP core maintains a LMFC counter that counts from 0 to (F × K/4)–1 and wraps around again. The LMFC counter resets within two link clock cycles after converter devices issue a common SYSREF frequency to all the transmitters and receivers. The SYSREF frequency must be the same for converter devices that are grouped and synchronized together.

Table 21.  Example of SYSREF Frequency CalculationIn this example, you can choose to perform one of the following options:
  • provide two SYSREF and device clock, where the ADC groups share both the device clock and SYSREF (18.75 MHz and 9.375 MHz)
  • provide one SYSREF (running at 9.375 MHz) and device clock for all the ADC and DAC groups because the SYSREF period in the DAC is a multiplication of n integer.
Group Configuration SYSREF Frequency
ADC Group 1 (2 ADCs)
  • LMF = 222
  • K = 16
  • Data rate = 6 Gbps
(6 GHz / 40) / (2 x 16 / 4) = 18.75 MHz
ADC Group 2 (2 ADCs)
  • LMF = 811
  • K = 32
  • Data rate = 6 Gbps
(6 GHz / 40) / (1 x 32 / 4) = 18.75 MHz
DAC Group 3 (2 DACs)
  • LMF = 222
  • K = 16
  • Data rate = 3 Gbps
(3 GHz / 40) / (2 x 16 / 4) = 9.375 MHz

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