JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/18/2022
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4.1.1.2. TX ILAS

When lane alignment sequence is enabled through the csr_lane_sync_en register, the ILAS sequence is transmitted after the CGS phase. The ILAS phase takes up four multiframes. For Subclass 0 mode, you can program the CSR (csr_ilas_multiframe) to extend the ILAS phase to a maximum of 256 multiframes before transitioning to the encoded user data phase. The ILAS data is not scrambled regardless of whether scrambling is enabled or disabled.

The multiframe has the following structure:

  • Each multiframe starts with a /R/ character (K28.0) and ends with a /A/ character (K28.3)
  • The second multiframe transmits the ILAS configuration data. The multiframe starts with /R/ character (K28.0), followed by /Q/ character (K28.4), and then followed by the link configuration data, which consists of 14 octets as illustrated in the table below. It is then padded with dummy data and ends with /A/ character (K28.3), marking the end of multiframe.
  • Dummy octets are an 8-bit counter and is always reset when it is not in ILAS phase.
  • For a configuration of more than four multiframes, the multiframe follows the same rule above and is padded with dummy data in between /R/ character and /A/ character.
Table 20.   Link Configuration Data Transmitted in ILAS Phase
Configuration Octet Bits Description
MSB 6 5 4 3 2 1 LSB
0 DID[7:0] DID = Device ID
1 ADJCNT[3:0] BID[3:0] ADJCNT = Number of adjustment resolution steps 21

BID = Bank ID

2 0 ADJDIR PHADJ LID[4:0]

ADJDIR = Direction to adjust DAC LMFC 21

PHADJ = Phase adjustment request 21

LID = Lane ID

3 SCR 0 0 L[4:0]

SCR = Scrambling enabled/disabled

L = Number of lanes per device (link)

4 F[7:0] F = Number of octets per frame per lane
5 0 0 0 K[4:0] K = Number of frames per multiframe
6 M[7:0] M = Number of converters per device
7 CS[1:0] 0 N[4:0]

CS = Number of control bits per sample

N = Converter resolution

8 SUBCLASSV[2:0] N_PRIME[4:0]

SUBCLASSV = Subclass version

N_PRIME = Total bits per sample

9 JESDV[2:0] S[4:0]

JESDV = JESD204 version

S = Number of samples per converter per frame

10 HD 0 0 CF[4:0]

HD = High Density data format

CF = Number of control words per frame clock per link

11 RES1[7:0] RES1 = Reserved. Set to 8'h00
12 RES2[7:0] RES2 = Reserved. Set to 8'h00
13 FCHK[7:0]

FCHK is the modulus 256 of the sum of the 13 configuration octets above.

For Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria V, Cyclone V, and Stratix V devices, if you change any of the octets during run time, make sure to update the new FCHK value in the register.

The JESD204B TX IP core also supports debug feature to continuously stay in ILAS phase without exiting. You can enable this feature by setting the bit in csr_ilas_loop register. There are two modes of entry:

  • RX asserts SYNC_N and deasserts it after CGS phase. This activity triggers the ILAS phase and the CSR stays in ILAS phase indefinitely until this setting changes.
  • Link reinitialization through CSR is initiated. The JESD204B IP core transmits /K/ character and causes the RX converter to enter CGS phase. After RX deasserts SYNC_N, the CSR enters ILAS phase and stays in that phase indefinitely until this setting changes.

In ILAS loop, the multiframe transmission is the same where /R/ character (K28.0) marks the start of multiframe and /A/ character (K28.3) marks the end of multiframe, with dummy data in between. The dummy data is an increment of Dx.y.

21 Applies to Subclass 2 only.

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