JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/18/2022
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4.7.1. Register Access Type Convention

This table describes the register access type for Intel® FPGA IP cores.
Table 27.  Register Access Type and Definition
Access Type Definition
RO Software read only (no effect on write). The value is hard-tied internally to either '0' or '1' and does not vary.
RO/v Software read only (no effect on write). The value may vary.
RC
  • Software reads and returns the current bit value, then the bit is self-clear to 0.
  • Software reads also cause the bit value to be cleared to 0.
RW
  • Software reads and returns the current bit value.
  • Software writes and sets the bit to the desired value.
RW1C
  • Software reads and returns the current bit value.
  • Software writes 0 and have no effect.
  • Software writes 1 and clear the bit to 0, if the bit has been set to 1 by hardware.
  • Hardware sets the bit to 1.
  • Software clear has higher priority than hardware set.
RW1S
  • Software reads and returns the current bit value.
  • Software writes 0 and have no effect.
  • Software writes 1 and set the bit to 1.
  • Hardware clears the bit to 0, if the bit has been set to 1 by software.
  • Software set has higher priority than hardware clear.

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