JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/05/2023

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Document Table of Contents

4.2.1. RX Data Link Layer

The JESD204B IP core RX data link layer buffers incoming user data on all lanes until the RX elastic buffers can be released. Special character substitution are done in the TX link so that the RX link can execute frame and lane alignment monitoring based on the JESD204B specification.