JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Document Table of Contents

5. JESD204B IP Deterministic Latency Implementation Guidelines

Subclass 1 and Subclass 2 modes support deterministic latency. This section describes the features available in the JESD204B IP that you can use to achieve Subclass 1 deterministic latency in your design. This section also covers some best practices for Subclass 1 implementation like constraining the incoming SYSREF signal and maintaining deterministic latency during link reinitialization.

Features available:

  • Programmable RBD offset.
  • Programmable LMFC offset.

Did you find the information on this page useful?

Characters remaining:

Feedback Message