JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

3.6.3. Compiling the JESD204B IP Core Design

Refer to the JESD204B IP Design Considerations before compiling the JESD204B IP core design.

To compile your design, click Start Compilation on the Processing menu in the Intel® Quartus® Prime software. You can use the generated .ip or .qip file to include relevant files into your project.

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