JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/18/2022
Document Table of Contents

2.5. JESD204B IP Configuration

Table 5.   JESD204B IP Configuration
Symbol Description Value
L Number of lanes per converter device 1-8
M Number of converters per device 1-256
F Number of octets per frame
  • 1–256 (for Intel® Stratix® 10 devices only)
  • 1, 2, 4–256 (for non Intel® Stratix® 10 devices)
S Number of transmitted samples per converter per frame 1-32
N Number of conversion bits per converter 1-32
N' Number of transmitted bits per sample (JESD204 word size, which is in nibble group) 1-32
K Number of frames per multiframe 17/F ≤ K ≤ 32 ; 1-32
CS Number of control bits per conversion sample 0-3
CF Number of control words per frame clock period per link 0-32
HD High Density user data format 0 or 1
LMFC Local multiframe clock (F × K /4) link clock counts 1
1 The value of F x K must be divisible by 4.

Did you find the information on this page useful?

Characters remaining:

Feedback Message