JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Document Table of Contents

6.3. SPI Programming

The SPI interface configures the converter. Hence, it is important to check the SPI programming sequence and register bit settings for the converter. If you use the MIF to store the SPI register settings of the converter, mistakes may occur when modifying the MIF, for example, setting a certain bit to "1" instead of "0", missing or extra bits in a MIF content row.

Check these items:

  • For example, in the ADI AD9250 converter, Intel® recommends that you first perform register bit setting for the scramble (SCR) or lane (L) register at address 0x6E before setting the quick configuration register at address 0x5E.
  • Determine that each row of the MIF has the same number of bits as the data width of the ROM that stores the MIF.

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