JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/18/2022
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3.8.4. Timing Constraints For Input Clocks

When you generate the JESD204B IP variation, the Intel® Quartus® Prime software generates a Synopsys Design Constraints File (.sdc) that specifies the timing constraints for the input clocks to your IP.

When you generate the JESD204B IP, your design is not yet complete and the JESD204B IP is not yet connected in the design. The final clock names and paths are not yet known. Therefore, the Intel® Quartus® Prime software cannot incorporate the final signal names in the .sdc file that it automatically generates. Instead, you must manually modify the clock signal names in this file to integrate these constraints with the timing constraints for your full design.

This section describes how to integrate the timing constraints that the Intel® Quartus® Prime software generates with your IP into the timing constraints for your design.

The Intel® Quartus® Prime software automatically generates the altera_jesd204.sdc file that contains the JESD204B IP's timing constraints.

Three clocks are created at the input clock port:
  • JESD204B TX IP:
    • txlink_clk
    • reconfig_to_xcvr[0] (for Arria® V, Cyclone® V, and Stratix® V devices only)
    • reconfig_clk (for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices only)
    • tx_avs_clk
  • JESD204B RX IP:
    • rxlink_clk
    • reconfig_to_xcvr[0] (for Arria® V, Cyclone® V, and Stratix® V devices only)
    • reconfig_clk (for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices only)
    • rx_avs_clk
In a functional system design, these clocks (except for reconfig_to_xcvr[0] clock) are typically provided by the core PLL.

In the .sdc file for your project, make the following command changes:

  • Specify the PLL clock reference pin frequency using the create_clock command.
  • Derive the PLL generated output clocks from the PLL Intel® FPGA IP (for Arria V, Cyclone V and Stratix V) or IOPLL Intel® FPGA IP (for Intel® Arria® 10 and Intel® Cyclone® 10 GX) using the derive_pll_clocks command.
  • For Intel® Stratix® 10 devices, Intel® FPGA IOPLL IP core has SDC file which derives the PLL clocks based on your PLL configurations. You need not add the derive_pll_clocks command into your top level SDC file."
  • Comment out the create_clock commands for the txlink_clk, reconfig_to_xcvr[0] or reconfig_clk, and tx_avs_clk, rxlink_clk, and rx_avs_clk clocks in the altera_jesd204.sdc file.
  • Identify the base and generated clock name that correlates to the txlink_clk, reconfig_clk, and tx_avs_clk, rxlink_clk, and rx_avs_clk clocks using the report_clock command.
  • Describe the relationship between base and generated clocks in the design using the set_clock_groups command.

After you complete your design, you must modify the clock names in your .sdc file to the full-design clock names, taking into account both the IP instance name in the full design, and the design hierarchy. Be careful when adding the timing exceptions based on your design, for example, when the JESD204B IP handles asynchronous timing between the txlink_clk, rxlink_clk, pll_ref_clk, tx_avs_clk, rx_avs_clk, and reconfig_clk (for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices only) clocks.

The table below shows an example of clock names in the altera_jesd204.sdc and input clock names in the user design. In this example, there is a dedicated input clock for the transceiver TX PLL and CDR at the refclk pin. The device_clk is the input to the core PLL clkin pin. The IP and transceiver Avalon® memory-mapped interfaces have separate external clock sources with different frequencies.

Table 13.  Example A
Original clock names in altera_jesd204.sdc User design input clock names Frequency (MHz) Recommended SDC timing constraint
tx_pll_ref_clk xcvr_tx_rx_refclk 250

create_clock -name xcvr_tx_rx_refclk -period 4.0 [get_ports xcvr_tx_rx_refclk ]

create_clock -name device_clk -period 8.0 [get_ports device_clk]

create_clock -name jesd204_avs_clk -period 10.0 [get_ports jesd204_avs_clk]

create_clock -name phy_mgmt_clk -period 13.3 [get_ports phy_mgmt_clk]

derive_pll_clocks

set_clock_groups -asynchronous \

-group {xcvr_tx_rx_refclk \

<base and generated clock names as reported by report_clock commands> \

} \

-group {device_clk \

<base and generated clock names as reported by report_clock commands> \

} \

-group {jesd204_avs_clk} \

-group {phy_mgmt_clk \

<base and generated clock names as reported by report_clock commands> \

}

rx_pll_ref_clk
txlink_clk device_clk 125
rxlink_clk
tx_avs_clk jesd204_avs_clk 100
rx_avs_clk
reconfig_clk 16 phy_mgmt_clk 75

However, if your design requires you to connect the rx_avs_clk and reconfig_clk to the same clock, you need to put them in the same clock group.

The table below shows an example where the device_clk in this design is an input into the transceiver refclk pin. The IP's Avalon® memory-mapped interface shares the same clock source as the transceiver management clock.

Table 14.  Example B
Original clock names in altera_jesd204.sdc User design input clock names Frequency (MHz) Recommended SDC timing constraint
tx_pll_ref_clk device_clk 125

create_clock -name device_clk -period 8.0 [get_ports device_clk]

create_clock -name mgmt_clk -period 10.0 [get_ports mgmt_clk]

derive_pll_clocks

set_clock_groups -asynchronous \

-group {device_clk \

<base and generated clock names as reported by report_clock commands> \

} \

-group {mgmt_clk \

<base and generated clock names as reported by report_clock commands> \

}

rx_pll_ref_clk
txlink_clk
rxlink_clk
tx_avs_clk mgmt_clk 100
rx_avs_clk
reconfig_clk 17
16 For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 only.
17 For Intel® Agilex™ , Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Arria® 10 only.

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