JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

4.2. Receiver

The receiver block, which interfaces to ADC devices, receives the serial streams from one or more TX blocks and converts the streams into one or more sample streams.

The receiver performs the following functions:

  • Data deserializer
  • 8B/10B decoding
  • Lane alignment
  • Character replacement
  • Data descrambling
Figure 13. Receiver Data Path Block Diagram


The receiver block includes the following modules:
  • RX CSR—manages the configuration and status registers.
  • RX_CTL—manages the SYNC_N signal, state machine that controls the data link layer states, LMFC, and also the buffer release, which is crucial for deterministic latency throughout the link.
  • RX Scrambler and Data Link Layer—takes in 32 bits of data that decodes the ILAS, performs descrambling, character replacement as per the JESD204B specification, and error detection (code group error, frame and lane realignment error).

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