4.4.5. Transceiver Calibration Clock Source
You must provide a 25, 100, or 125 MHz free-running and stable clock to the OSC_CLK_1 pin. The FPGA device's Internal Oscillator cannot be used for transceiver calibration. Do not select this clock source as the Configuration clock source in the Intel® Quartus® Prime software settings. For Intel® Stratix® 10 L-tile and H-tile devices, refer to the Calibration section in the L- and H-Tile Transceiver PHY User Guide.
- Open your project in the Intel® Quartus® Prime software.
- Right-click the device part number in your Intel® Quartus® Prime project.
- Select Device, and click on Device and Options.
- Select General from the Category pane.
- Select 25 MHz OSC_CLK_1 pin, 125 MHz OSC_CLK_1 pin, or 100 MHz OSC_CLK_1 pin from the Configuration clock source drop-down list.
- Click OK.
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