JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/05/2023
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4.4.4. Clock Correlation

This section describes the clock correlation between the device clock, link clock, frame clock, and local multiframe clock.

Example 1

Targeted Device with LMF=222, K=16 and Data rate = 6.5 Gbps

Device Clock Selected = 325 MHz (obtained during IP core generation)

Link Clock = 6.5 GHz/40 = 162.5 MHz

Frame Clock = 6.5 GHz/(10x2) = 325 MHz

Local Multiframe Clock = 325 MHz / 16 = 20.3125 MHz

SYSREF Frequency = Local Multiframe Clock / n; (n = integer; 1, 2, …)

Local Multiframe Clock Counter = (F × K/4) = (2×16/4) = 8 link clocks 24

Example 2

Targeted Device with LMF=244, K=16 and Data rate = 5.0 Gbps

Device Clock Selected = 125 MHz (obtained during IP core generation)

Link Clock = 5 GHz/40 = 125 MHz 25

Frame Clock = 5 GHz /(10×4) = 125 MHz 25

Local Multiframe Clock = 125 MHz / 16 = 7.8125 MHz

SYSREF Frequency = Local Multiframe Clock / n; (n = integer; 1, 2, …)

Local Multiframe Clock Counter = (F × K/4) = (4×16/4) = 16 link clocks 24

Example 3

Targeted Device with LMF=421, K=32 and Data rate = 10.0 Gbps

Device Clock Selected = 250 MHz (obtained during IP core generation)

Link Clock = 10 GHz/40 = 250 MHz

Frame Clock = 10 GHz/(10×1) = 1 GHz 26

Local Multiframe Clock = 1 GHz / 32 = 31.25 MHz

SYSREF Frequency = Local Multiframe Clock / n; (n = integer; 1, 2, …)

Local Multiframe Clock Counter = (F × K/4) = (1×32/4) = 8 link clocks 24

Example 4 (When F=3, for Intel® Stratix® 10 devices only)

Targeted Device with LMF=883, K=32 and Data rate = 12.0 Gbps

Device Clock Selected = 300 MHz (obtained during IP core generation)

Link Clock = 12 GHz/40 = 300 MHz

Frame Clock = 12 GHz/(10×3) = 400 MHz 27

Local Multiframe Clock = 400 MHz / 32 = 12.5 MHz

SYSREF Frequency = Local Multiframe Clock / n; (n = integer; 1, 2, …)

Local Multiframe Clock Counter = (F × K/4) = (3×32/4) = 24 link clocks 24

24 Eight link clocks mean that the local multiframe clock counts from values 0 to 7 and then loops back to 0.
25 The link clock and frame clock are running at the same frequency. You only need to generate one clock from the Intel® FPGA PLL or Intel® FPGA IO PLL IP core.
26 In this example, the frame clock may not be able to run up to 1 GHz in the FPGA fabric. The JESD204B transport layer in the design example supports running the data stream of half rate (1 GHz/2 = 500 MHz), at two times the data bus width or of quarter rate (1GHz/4 = 250 MHz), at four times the data bus width.
27 The JESD204B transport layer in the design example runs the data stream at half rate (400 MHz/2 = 200 MHz), two times the data bus width.