JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/18/2022
Public
Document Table of Contents

3.8.1. Integrating the JESD204B IP in Platform Designer

You can integrate the JESD204B IP with other Platform Designer components within Platform Designer.

You can connect standard interfaces like clock, reset, Avalon® memory-mapped, Avalon® streaming, HSSI bonded clock, HSSI serial clock, and interrupt interfaces within Platform Designer. However, for conduit interfaces, you are advised to export all those interfaces and handle them outside of Platform Designer. 15 This is because conduit interfaces are not part of the standard interfaces. Thus, there is no guarantee on compatibility between different conduit interfaces.

Note: The Transport Layer provided in this JESD204B IP design example is not supported in Platform Designer. Therefore, you must export all interfaces that connect to the Transport Layer (for example, jesd204_tx_link interface) and connect them to a transport layer outside of Platform Designer.
Figure 8. Example of Connecting JESD204B IP with Other Platform Designer Components in Platform Designer Figure shows an example of how you connect the IP with other Platform Designer components in Platform Designer.
15 You can also connect conduit interfaces within Platform Designer but you must create adapter components to handle all the incompatibility issues like incompatible signal type and width.

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