JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy

The Signal Tap and system console are very useful tools in debugging the JESD204B link related issues. The Signal Tap provides a dynamic view of signals.

For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices, the Intel® Quartus® Prime software generates two files, build_stp.tcl and <ip_core_name>.xml. You can use these files to generate a Signal Tap file with probe points matching your design hierarchy.

The Intel® Quartus® Prime software stores these files in the <debug stp directory>. The <debug stp directory> is defined based on JESD204B wrapper and data path.

File Directory
JESD204B Wrapper Data Path Debug stp directory
Both Base and PHY Transmitter/Duplex <ip_variant_name>/altera_jesd204_tx_mlpcs_<Quartus_version>/synth/debug/stp
Receiver <ip_variant_name>/altera_jesd204_rx_mlpcs_<Quartus_version>/synth/debug/stp
Base only Transmitter <ip_variant_name>/altera_jesd204_tx_<Quartus_version>/synth/debug/stp
Receiver <ip_variant_name>/altera_jesd204_rx_<Quartus_version>/synth/debug/stp
Synthesize your design by running Analysis and Synthesis in the Intel® Quartus® Prime software.
  1. Run analysis and synthesis.
  2. Then open the Tcl console by clicking View > Utility Windows > Tcl Console.
  3. Navigate to the <debug stp directory> as shown in .
  4. Type the following command in the Tcl console:
    source build_stp.tcl
  5. To generate the STP file, type the following command:
    main -stp_file <stp file name>.stp -xml_file 
    <xml_file name>.xml -mode build
    The <stp file name>.stp file is generated in the <debug stp directory>.
  6. The software generation script may not assign the Signal Tap acquisition clock in the <stp file name>.stp file. Consequently, the Intel® Quartus® Prime software automatically creates a clock pin (auto_stp_external_clock) for each instance. To assign an acquisition clock for the generated STP file, Intel® recommends that you perform the following assignments:
    JESD204B Duplex & Simplex (Both Base & PHY) or (PHY only) IP core:-
    • For rx_link instance, assign the rxlink_clk signal.
    • For tx_link instance, assign the txlink_clk signal.
    • For all supported devices, except Intel® Stratix® 10 E-tile devices:

      For rx_phy and tx_phy instances, assign the input clock of the transceiver reset controller.

    • For Intel® Stratix® 10 E-tile devices:
      For rx_phy and tx_phy instances, assign rxphy_clk[0] and txphy_clk[0] as the acquisition clock. Then, add the following set_false_path constraint in the SDC script.
      set_false_path -from 
      <instance_name>|inst_phy|inst_xcvr|*counter_*x_ready|r_reset -to 
      auto_fab*sld_signaltap_inst*
    Note: The PHY signals are different for Intel® Stratix® 10 E-tile devices. Remove the irrelevant signals and add the Intel® Stratix® 10 E-tile device PHY signals into the Signal Tap Logic Analyzer. Refer to Removing Irrelevant Signals and Adding E-Tile PHY Signals.
    JESD204B Simplex (Base only) IP core:-
    • For rx_link instance, assign the rxlink_clk signal.
    • For tx_link instance, assign the txlink_clk signal.
    Note: The GUI parameter editor allows you to choose the appropriate instance for each IP core name if your design contains more than one JESD204B instances. For simplex core, you need to choose the RX instance followed by TX instance to generate the proper STP file.
  7. Click Save to save the modified STP. A dialog box pops up with a message "Do you want to enable Signal Tap File "<stp file name>" for the current project?". Click Yes. Then, compile your design.
  8. To program the FPGA, click Tools > Programmer.
  9. Open the generated STP file again if it has closed after step 6.
  10. To observe the state of your IP core, click Run Analysis in the Signal Tap Logic Analyzer.
    You may see signals or Signal Tap instances that are red, indicating they are not available in your design. In most cases, you can safely ignore these signals and instances because the software generates wider buses and certain instances that your design does not include.

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