JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/18/2022
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6.4. Converter and FPGA Operating Conditions

The transceiver channels at the converter and FPGA are bounded by minimum and maximum data rate requirements. Always check the most updated device data sheet for this info. For example, the Arria V GT device has a minimum data rate of 611 Mbps.

Ensure that the sampling rate of the converter is within the minimum and maximum requirements. For example, the ADC AD9250 has a minimum sampling rate of 40 Msps. For L = 2, M = 1 configuration, the minimum data rate of this ADC is calculated this way:



The minimum data rate for the JESD204B link is effectively 611 Mbps.

Check these items:

  • Reduce the data rate or sampling clock frequency if your targeted operating requirement does not work.
  • Verify the minimum and maximum data rate requirements in the device manufacturer's data sheet.

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