JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/05/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.8. JESD204B IP Design Considerations

You must be aware of the following conditions when integrating the JESD204B IP in your design:
  • Integrating the IP in Platform Designer
  • Pin assignments
  • Adding external transceiver PLL
  • Timing constraints for the input clock