JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

3.8. JESD204B IP Design Considerations

You must be aware of the following conditions when integrating the JESD204B IP in your design:
  • Integrating the IP in Platform Designer
  • Pin assignments
  • Adding external transceiver PLL
  • Timing constraints for the input clock

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