JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

2. About the JESD204B Intel® FPGA IP

The JESD204B Intel® FPGA IP is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to FPGA devices. This unidirectional serial interface runs at a maximum data rate of 17.4 Gbps. This protocol offers higher bandwidth, low I/O count and supports scalability in both number of lanes and data rates. The JESD204B Intel® FPGA IP addresses multi-device synchronization by introducing Subclass 1 and Subclass 2 to achieve deterministic latency.
Note: The full product name, JESD204B Intel® FPGA IP, is shortened to JESD204B IP in this document.

The JESD204B IP incorporates:

  • Media access control (MAC)—data link layer (DLL) block that controls the link states and character replacement.
  • Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.

The JESD204B IP does not incorporate the Transport Layer (TL) that controls the frame assembly and disassembly. The TL and test components are provided as part of a design example component where you can customize the design for different converter devices.

Figure 1. Typical System Application for JESD204B IPThe JESD204B IP uses the Avalon® streaming source and sink interfaces, with unidirectional flow of data, to transmit and receive data on the FPGA fabric interface.


Key features of the JESD204B IP:
  • Data rate of up to 19.2 Gbps (characterization up to 12.5 G)
  • Run-time JESD204B parameter configuration (L, M, F, S, N, K, CS, CF)
  • MAC and PHY partitioning for portability
  • Subclass 0 mode for backward compatibility to JESD204A
  • Subclass 1 mode for deterministic latency support (using SYSREF) between the ADC/DAC and logic device
  • Subclass 2 mode for deterministic latency support (using SYNC_N) between the ADC/DAC and logic device
  • Multi-device synchronization

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