3.8.3. Adding External Transceiver PLLs
The JESD204B IP core variations that target an Intel® Stratix® 10 L-tile, Intel® Stratix® 10 H-tile, Intel® Arria® 10, or Intel® Cyclone® 10 GX FPGA device, require external transceiver PLLs for compilation. Select medium bandwidth for the PLL settings.
JESD204B IP variations that target an Arria V, Cyclone V, or Stratix V FPGA device contain transceiver PLLs. Therefore, no external PLLs are required for compilation.
Intel recommends that you follow the PLL recommendations in the respective Transceiver PHY user guides based on the data rates.
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