JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

3.8.3. Adding External Transceiver PLLs

The JESD204B IP core variations that target an Intel® Stratix® 10 L-tile, Intel® Stratix® 10 H-tile, Intel® Arria® 10, or Intel® Cyclone® 10 GX FPGA device, require external transceiver PLLs for compilation. Select medium bandwidth for the PLL settings.

Note: For Intel® Agilex™ and Intel® Stratix® 10 E-tile devices, the transceiver PLL is within the transceiver itself; so the design does not require external PLLs.

JESD204B IP variations that target an Arria V, Cyclone V, or Stratix V FPGA device contain transceiver PLLs. Therefore, no external PLLs are required for compilation.

Intel recommends that you follow the PLL recommendations in the respective Transceiver PHY user guides based on the data rates.

Note: The PMA width is 20 bits for Hard PCS and 40 bits for Soft PCS.

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