JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/18/2022
Public
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3.11.1.1. Generating the Testbench Simulation Model

To generate the testbench simulation model, execute the generated script (gen_sim_verilog.tcl or gen_sim_vhdl.tcl) located in the <example_design_directory>/ip_sim folder.

To run the Tcl script using the Intel® Quartus® Prime software, follow these steps:

  1. Launch the Intel® Quartus® Prime software.
  2. On the View menu, click Utility Windows > Tcl Console.
  3. In the Tcl Console, type cd <example_design_directory>/ip_sim to go to the specified directory.
  4. Type source gen_sim_verilog.tcl (Verilog) or source gen_sim_vhdl.tcl (VHDL) to generate the simulation files.

To run the Tcl script using the command line, follow these steps:

  1. Obtain the Intel® Quartus® Prime software resource.
  2. Type cd <example_design_directory>/ip_sim to go to the specified directory.
  3. Type quartus_sh -t gen_sim_verilog.tcl (Verilog) or quartus_sh -t gen_sim_vhdl.tcl (VHDL) to generate the simulation files.

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