JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/18/2022
Public
Document Table of Contents

4.1. Transmitter

The transmitter block, which interfaces to DAC devices, takes one of more digital sample streams and converts them into one or more serial streams.

The transmitter performs the following functions:

  • Data scrambling
  • Frame or lane alignment
  • Character generation
  • Serial lane monitoring
  • 8B/10B encoding
  • Data serializer
Figure 12. Transmitter Data Path Block Diagram


The transmitter block consists of the following modules:
  • TX CSR—manages the configuration and status registers.
  • TX_CTL—manages the SYNC_N signal, state machine that controls the data link layer states, LMFC, and also the deterministic latency throughout the link.
  • TX Scrambler and Data Link Layer—takes in 32 bits of data that implements the Initial Lane Alignment Sequence (ILAS), performs scrambling, lane insertion and frame alignment of characters.

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