JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/05/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.4. Link Reinitialization

The JESD204B TX and RX IP core support link reinitialization.

There are two modes of entry for link reinitialization:

  • Hardware initiated link reinitialization:
    • For TX, the reception of SYNC_N for more than five frames and nine octets triggers link reinitialization.
    • For RX, the loss of code group synchronization, frame alignment and lane alignment errors cause the IP core to assert SYNC_N and request for link reinitialization.
  • Software initiated link reinitialization—both the TX and RX IP core allow software to request for link reinitialization.
    • For TX, the IP core transmits /K/ character and wait for the receiver to assert SYNC_N to indicate that it has entered CS_INIT state.
    • For RX, the IP core asserts SYNC_N to request for link reinitialization.

Hardware initiated link reinitialization can be globally disabled through the csr_link_reinit_disable register for debug purposes.

Hardware initiated link reinitialization can be issued as interrupt depending on the error type and interrupt error enable. If lane misalignment has been detected as a result of a phase change in local timing reference, the software can rely on this interrupt trigger to initiates a LMFC realignment. The realignment process occurs by first resampling SYSREF and then issuing a link reinitialization request.