JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 5/18/2022
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3.11. JESD204B IP Testbench

The JESD204B IP includes a testbench to demonstrate a normal link-up sequence for the JESD204B IP with a supported configuration. The testbench also provides an example of how to control the JESD204B IP interfaces.

The testbench instantiates the JESD204B IP in duplex mode and connects with the Intel® FPGA Transceiver PHY Reset Controller IP. Some configurations are preset and are not programmable in the JESD204B IP testbench. For example, the JESD204B IP always instantiates in duplex mode even if RX or TX mode is selected in the JESD204B parameter editor.

Table 17.  Preset Configurations for JESD204B IP Testbench
Configuration Preset Value
JESD204B Wrapper Base and PHY (MAC and PHY)
Data Path Simplex TX and simplex RX
PLL/CDR Reference Clock Frequency20 For Base only, or Simplex TX variants:
  • Data_rate/20 (if you turn on Enabled Hard PCS)
  • Data_rate/40 (if you turn on Enabled Soft PCS)
  • Data_rate/80 (if you turn on Enabled PMA Direct)
Link Clock
  • Data_rate/40
AVS Clock 100 MHz
Figure 9.  JESD204B IP Testbench Block DiagramThe external ATX PLL is present only in the JESD204B IP testbench targeting Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 L-tile and H-tile devices. For Intel® Agilex™ and Intel® Stratix® 10 E-tile devices, the Transceiver PHY Reset Controller is within the transceiver block.


20 For the ATX PLL supported range of reference clock frequencies, refer to the respective device datasheet.

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