JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

4.3.1.3. Subclass 2 Operating Mode

The JESD204B IP core maintains a LMFC counter that counts from 0 to (F × K/4)–1 and wraps around again. The LMFC count starts upon reset and the logic device always acts as the timing master. To support Subclass 2 for multi-link device, you must deassert the resets for all JESD204B IP core links synchronously at the same clock edge. This deassertion ensures that the internal LMFC vaunter is aligner across multi-link. The converters adjust their own internal LMFC to match the master's counter. The alignment of LMFC within the system relies on the correct alignment of SYNC_N signal deassertion at the LMFC boundary.

The alignment of LMFC to RX logic is handled within the TX converter. The RX logic releases SYNC_N at the LMFC tick and the TX converter adjust its internal LMFC to match the RX LMFC.

For the alignment of LMFC to the TX logic, the JESD204B TX IP core samples SYNC_N from the DAC receiver and reports the relative phase difference between the DAC and TX logic device LMFC in the TX CSR (dbg_phadj, dbg_adjdir, and dbg_adjcnt). Based on the reported value, you can calculate the adjustment required. Then, to initiate the link reinitialization through the CSR, set the value in the TX CSR (csr_phadj, csr_adjdir, and csr_adjcnt). The values on the phase adjustment are embedded in bytes 1 and 2 of the ILAS sequence that is sent to the DAC during link initialization. On the reception of the ILAS, the DAC adjusts its LMFC phase by step count value and sends back an error report with the new LMFC phase information. This process may be repeated until the LMFC at the DAC and the logic device are aligned.

Table 22.   dbg_phadj, dbg_adjdir and dbg_adjcnt Values for Different SYNC_N Deassertions
Case SYNC_N Signal Deassertion dbg_phadj Value dbg_adjdir Value dbg_adjcnt Value
1 Happens at LMFC boundary23 0
2 Happens at LMFC count value that is equals or less than half of FxK/4 value 1 0 Number of link clock cycles from the LMFC boundary to the detection of SYNC_N signal deassertion
3 Happens at LMFC count value that is more than half of FxK/4 value 1 1 Number of link clock cycles from detection of the SYNC_N signal deassertion to the next LMFC boundary
Figure 15. Timing Diagram Example for Case 1
Figure 16. Timing Diagram Example for Case 2
Figure 17. Timing Diagram Example for Case 3
23 No adjustment is required.

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