3.11.2. Testbench Simulation Flow
The JESD204B testbench simulation flow:
- At the start, the system is under reset (all the components are in reset).
- After 100 ns, the Transceiver Reset Controller IP core power up and wait for the tx_ready and rx_ready signal from the Transceiver Reset Controller IP to assert.
- After 500 ns (all devices except Intel Agilex® 7 and Intel® Stratix® 10 E-tile) or 1500 ns ( Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices), the reset signal of the JESD204B TX Avalon® memory-mapped interface is released (go HIGH). At the next positive edge of the link_clk signal, the JESD204B TX link powers up by releasing its reset signal.
- The JESD204B TX link starts transmitting K28.5 characters.
- The reset signal of the JESD204B RX Avalon® memory-mapped interface is released (go HIGH). At the next positive edge of the link_clk signal, the JESD204B RX link powers up by releasing its reset signal.
- Once the link is out of reset, a SYSREF pulse is generated to reset the LMFC counter inside both the JESD204B TX and RX IP core.
- When the txlink_ready signal is asserted, the packet generator starts sending packets to the TX datapath.
- The packet checker starts comparing the packet sent from the TX datapath and received at the RX datapath after the rxlink_valid signal is asserted.
- The testbench reports a pass or fail when all the packets are received and compared.
The testbench concludes by checking that all the packets have been received.
If no error is detected, the testbench issues a TESTBENCH PASSED message stating that the simulation was successful. If an error is detected, the testbench issues a TESTBENCH FAILED message to indicate that the testbench has failed.