JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

3.11.2. Testbench Simulation Flow

The JESD204B testbench simulation flow:

  1. At the start, the system is under reset (all the components are in reset).
  2. After 100 ns, the Transceiver Reset Controller IP core power up and wait for the tx_ready and rx_ready signal from the Transceiver Reset Controller IP to assert.
  3. After 500 ns (all devices except Intel® Agilex™ and Intel® Stratix® 10 E-tile) or 1500 ns ( Intel® Agilex™ and Intel® Stratix® 10 E-tile devices), the reset signal of the JESD204B TX Avalon® memory-mapped interface is released (go HIGH). At the next positive edge of the link_clk signal, the JESD204B TX link powers up by releasing its reset signal.
  4. The JESD204B TX link starts transmitting K28.5 characters.
  5. The reset signal of the JESD204B RX Avalon® memory-mapped interface is released (go HIGH). At the next positive edge of the link_clk signal, the JESD204B RX link powers up by releasing its reset signal.
  6. Once the link is out of reset, a SYSREF pulse is generated to reset the LMFC counter inside both the JESD204B TX and RX IP core.
  7. When the txlink_ready signal is asserted, the packet generator starts sending packets to the TX datapath.
  8. The packet checker starts comparing the packet sent from the TX datapath and received at the RX datapath after the rxlink_valid signal is asserted.
  9. The testbench reports a pass or fail when all the packets are received and compared.

The testbench concludes by checking that all the packets have been received.

If no error is detected, the testbench issues a TESTBENCH PASSED message stating that the simulation was successful. If an error is detected, the testbench issues a TESTBENCH FAILED message to indicate that the testbench has failed.

Note: For Intel® Stratix® 10 L-tile and H-tile devices, reset deassertion staggering of TX/RX analog and digital reset happens before the assertion of TX/RX ready. The reset staggering may incur long simulation time. You may observe the staggering of TX and RX reset through tx_analogreset_stat, tx_digitalreset_stat, rx_analogreset_stat, and rx_digitalreset_stat respectively.

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