JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

3.11.1.2. Simulating the IP Testbench

Note: VHDL is not supported in VCS* simulator.
Table 18.  Simulation Setup Scripts

Simulator

File Directory

Script

ModelSim* - Intel® FPGA Edition/ ModelSim* - Intel® FPGA Starter Edition <example_design_directory>/ip_sim/testbench/setup_scripts/mentor msim_setup.tcl
QuestaSim* simulator
Synopsys VCS* simulator <example_design_directory>/ip_sim/testbench/setup_scripts/synopsys/vcs vcs_setup.sh
Synopsys VCS* MX simulator <example_design_directory>/ip_sim/testbench/setup_scripts/synopsys/vcsmx

vcsmx_setup.sh

synopsys_sim.setup

Aldec Riviera-PRO*
Note: Intel® Agilex™ and Intel® Stratix® 10 E-tile devices do not support this simulator.
<example_design_directory>/ip_sim/testbench/setup_scripts/aldec rivierapro_setup.tcl
Cadence Xcelium* Parallel simulator <example_design_directory>/ip_sim/testbench/setup_scripts/xcelium xcelium_setup.sh
Table 19.  Simulation Run Scripts

Simulator

File Directory

Script

ModelSim* - Intel® FPGA Edition/ ModelSim* - Intel® FPGA Starter Edition <example_design_directory>/ip_sim/testbench/mentor run_altera_jesd204_tb.tcl
QuestaSim* simulator
Synopsys VCS* simulator <example_design_directory>/ip_sim/testbench/synopsys/vcs run_altera_jesd204_tb.sh
Synopsys VCS* MX simulator <example_design_directory>/ip_sim/testbench/synopsys/vcsmx

run_altera_jesd204_tb.sh

Aldec Riviera-PRO*
Note: Intel® Agilex™ and Intel® Stratix® 10 E-tile devices do not support this simulator.
<example_design_directory>/ip_sim/testbench/aldec run_altera_jesd204_tb.tcl
Cadence Xcelium* Parallel simulator <example_design_directory>/ip_sim/testbench/xcelium run_altera_jesd204_tb.sh

To simulate the testbench design using the ModelSim* - Intel® FPGA Edition/ ModelSim* - Intel® FPGA Starter Edition or QuestaSim* simulator, follow these steps:

  1. Launch the ModelSim* - Intel® FPGA Edition/ ModelSim* - Intel® FPGA Starter Edition or QuestaSim* simulator.
  2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/<simulator name>.
  3. On the File menu, click Load > Macro file. Select run_altera_jesd204_tb.tcl. This file compiles the design and runs the simulation automatically, providing a pass or fail indication on completion.

To simulate the testbench design using the Aldec Riviera-PRO* simulator, follow these steps:

  1. Launch the Aldec Riviera-PRO* simulator.
  2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/<simulator name>.
  3. On the Tool menu, click Execute Macro. Select run_altera_jesd204_tb.tcl. This file compiles the design and runs the simulation automatically, providing a pass or fail indication on completion.

To simulate the testbench design using the VCS* , VCS* MX (in Linux), or Cadence simulators, follow these steps:

  1. Launch the Synopsys VCS* or VCS* MX, or Cadence Xcelium* Parallel simulator.
  2. On the File menu, click Change Directory > Select <example_design_directory>/ip_sim/testbench/<simulator name>.
  3. Run the run_altera_jesd204_tb.sh file. This file compiles the design and runs the simulation automatically, providing a pass or fail indication on completion.

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