JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/05/2023
Public

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4.2.1.5. ILAS Data

The JESD204B RX IP core captures 14 octets of link configuration data that are transmitted on the 2nd multiframe of the ILAS phase. The receiver waits for the reception of /Q/ character that marks the start of link configuration data and then latch it into ILAS octets, which are per lane basis. You can read the 14 octets captured in the link configuration data through the CSR. You need to first set the csr_ilas_data_sel register to select which link configuration data lane it is trying to read from. Then, proceed to read from the csr_ilas_octet register.