JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/05/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents Subclass 0 Operating Mode

The JESD204B IP core maintains a LMFC counter that counts from 0 to (F × K/4)–1 and wraps around again. The LMFC counter starts counting at the deassertion of SYNC_N signal from multiple DACs after synchronization. This is to align the LMFC counter upon transmission and can only be done after all the converter devices have deasserted its synchronization request signal.