JESD204B Intel® FPGA IP User Guide

ID 683442
Date 8/18/2022
Public
Document Table of Contents

2.5.1. Run-Time Configuration

The JESD204B IP allows run-time configuration of LMF parameters in all supported devices except for Intel® Stratix® 10. For Intel® Stratix® 10 devices, the JESD204B IP core must be parameterized according to your target converter device with the IP configurations shown in JESD204B Configurations Tab of Table 15

Note: For Intel® Stratix® 10 devices, run-time access for certain registers have been disabled. Refer to the TX and RX register map for more information.

The most critical parameters that must be set correctly during IP generation are the L and F parameters. Parameter L denotes the maximum lanes supported while parameter F denotes the size of the deskew buffer needed for deterministic latency. The hardware generates during parameterization, which means that run-time programmability can only fall back from the parameterized and generated hardware, but not beyond the parameterized IP core.

You can use run-time configuration for prototyping or evaluating the performance of converter devices with various LMF configurations. However, in actual production, Intel® recommends that you generate the JESD204B IP core with the intended LMF to get an optimized gate count.

For example, if a converter device supports LMF = 442 and LMF = 222, to check the performance for both configurations, you need to generate the JESD204B IP with maximum F and L, which is L = 4 and F = 2. During operation, you can use the fall back configuration to disable the lanes that are not used in LMF = 222 mode. You must ensure that other JESD204B configurations like M, N, S, CS, CF, and HD do not violate the parameter F setting. You can access the Configuration and Status Register (CSR) space to modify other configurations such as:

  • K (multiframe)
  • device and lane IDs
  • enable or disable scrambler
  • enable or disable character replacement

F Parameter

This parameter indicates how many octets per frame per lane that the JESD204B link is operating in.

  • Intel® Agilex™ and Intel® Stratix® 10 (L-tile, H-tile, and E-tile) devices support F = 1–256 (F = 3 available)
  • Intel® Cyclone® 10 GX , Intel® Arria® 10, Stratix® V, Arria® V, Arria® V GZ, and Cyclone® V devices support F = 1, 2, 4–256 (F = 3 not available)

To support the High Density (HD) data format, the JESD204B IP tracks the start of frame and end of frame because F can be either an odd or even number. The start of frame and start of multiframe wrap around the 32-bit data width architecture. The RX IP outputs the start of frame (sof[3:0]) and start of multiframe (somf[3:0]), which act as markers, using the Avalon® streaming data stream. Based on these markers, the transport layer build the frames.

In a simpler system where the HD data format is set to 0, the F will always be 1, 2, 4, 6, 8, and so forth. This simplifies the transport layer design, so you do not need to use the sof[3:0] and somf[3:0] markers.

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