JESD204B Intel® FPGA IP User Guide

ID 683442
Date 5/18/2022
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4.7. Registers

The JESD204B IP core supports a basic one clock cycle transaction bus. There is no support for burst mode and wait-state feature (the avs_waitrequest signal is tied to 0). The JESD204B IP core Avalon® memory-mapped slave interface has a data width of 32 bits and is implemented based on word addressing. The Avalon® memory-mapped slave interface does not support byte enable access.

Each write transfer has a writeWaitTime of 0 cycle while a read transfer has a readWaitTime of 1 cycle and readLatency of 1 cycle.

The following sections list the TX and RX core registers. The register address in the register map is written based on byte addressing. The Platform Designer interconnect automatically converts from byte to word addressing. You do not need to manually shift the address bus. If the Avalon® memory-mapped master interfaces to the IP core Avalon® memory-mapped slave without the Platform Designer interconnect, to perform byte to word addressing conversion, you are recommended to shift the Avalon® memory-mapped master address bus by 2 bits (divide by 4) when connecting to the IP core's Avalon® memory-mapped slave. In this connection, the Avalon® memory-mapped master address bit[2] connects to the IP core ( Avalon® memory-mapped slave) address bit[0], while the Avalon® memory-mapped master bit[9] connects to the IP core address bit[7].
Note: For Intel® Stratix® 10 devices, run-time access for certain registers have been disabled. Refer to the TX and RX register map for more information.

All registers that are Read-Writable must be protected to comply with Security Development Lifecycle (SDL) practices. You are required to perform the register access protection.

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