Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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6.9.2. XGMII RX Signals

The signals below are present in the following operating modes: 10G, 1G/10G, 1G/2.5G/10G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/10G, and 10M/100M/1G/2.5G/10G.

Table 47.  XGMII Receive Signals
Signal Condition Direction Width Description
xgmii_rx_data[]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Enable 10GBASE-R register mode disabled.

In 32 4-lane RX data bus. Lane 0 starts from the least significant bit.
  • Lane 0: xgmii_rx_data[7:0]
  • Lane 1: xgmii_rx_data[15:8]
  • Lane 2: xgmii_rx_data[23:16]
  • Lane 3: xgmii_rx_data[31:24]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Enable 10GBASE-R register mode enabled.

In 64

8-lane SDR XGMII receive data. This signal connects directly to the Native PHY IP core.

  • Lane 0: xgmii_rx_data[7:0]
  • Lane 1: xgmii_rx_data[15:8]
  • Lane 2: xgmii_rx_data[23:16]
  • Lane 3: xgmii_rx_data[31:24]
  • Lane 4: xgmii_rx_data[39:32]
  • Lane 5: xgmii_rx_data[47:40]
  • Lane 6: xgmii_rx_data[55:48]
  • Lane 7: xgmii_rx_data[63:56]
xgmii_rx_control[]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Enable 10GBASE-R register mode disabled.

In 4 Control bits for each lane in xgmii_rx_data[].
  • Lane 0: xgmii_rx_control[0]
  • Lane 1: xgmii_rx_control[1]
  • Lane 2: xgmii_rx_control[2]
  • Lane 3: xgmii_rx_control[3]

Use legacy Ethernet 10G MAC XGMII interface disabled.

Enable 10GBASE-R register mode enabled.

In 8

8-lane SDR XGMII receive control. This signal connects directly to the NativePHY IP core.

  • Lane 0: xgmii_rx_control[0]
  • Lane 1: xgmii_rx_control[1]
  • Lane 2: xgmii_rx_control[2]
  • Lane 3: xgmii_rx_control[3]
  • Lane 4: xgmii_rx_control[4]
  • Lane 5: xgmii_rx_control[5]
  • Lane 6: xgmii_rx_control[6]
  • Lane 7: xgmii_rx_control[7]
xgmii_rx_valid

Use legacy Ethernet 10G MAC XGMII interface disabled.

(Enable 10GBASE-R register mode or Speed is set to 100M/100M/1G/2.5G/5G/10G (USXGMII))

In 1 When asserted, indicates that the data and control buses are valid.
xgmii_rx[] Use legacy Ethernet 10G MAC XGMII interface enabled. In 72

8-lane SDR XGMII receive data and control bus. Each lane contains 8 data plus 1 control bits. The signal mapping is compatible with the 64-bit MAC.

  • Lane 0 data: xgmii_rx[7:0]
  • Lane 0 control: xgmii_rx[8]
  • Lane 1 data: xgmii_rx[16:9]
  • Lane 1 control: xgmii_rx[17]
  • Lane 2 data: xgmii_rx[25:18]
  • Lane 2 control: xgmii_rx[26]
  • Lane 3 data: xgmii_rx[34:27]
  • Lane 3 control: xgmii_rx[35]
  • Lane 4 data: xgmii_rx[43:36]
  • Lane 4 control: xgmii_rx[44]
  • Lane 5 data: xgmii_rx[52:45]
  • Lane 5 control: xgmii_rx[53]
  • Lane 6 data: xgmii_rx[61:54]
  • Lane 6 control: xgmii_rx[62]
  • Lane 7 data: xgmii_rx[70:63]
  • Lane 7 control: xgmii_rx[71]
link_fault_status_xgmii_rx_data[] Out 2 The following values indicate the link fault status:
  • 0x0 = No link fault
  • 0x1 = Local fault
  • 0x2 = Remote fault