Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
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Document Table of Contents

5.1. Register Map

Table 20.  Register Map
Word Offset Purpose Variation
0x0000: 0x000F Reserved
0x0010: 0x0011 Primary MAC Address MAC TX, MAC RX
0x0012: 0x001D Reserved
0x001F MAC Reset Control Register  
0x0020: 0x003F TX Configuration and Status Registers MAC TX
0x0040: 0x005F TX Flow Control Registers MAC TX
0x0060: 0x006F Reserved
0x0070 TX Unidirectional Control Register MAC TX
0x0071: 0x009F Reserved
0x00A0: 0x00FF RX Configuration and Status Registers MAC RX
0x0100: 0x010C TX Timestamp Registers MAC TX
0x0120: 0x012C RX Timestamp Registers MAC RX
0x0140: 0x023F Statistics Registers MAC TX, MAC RX
0x0240: 0x0241 ECC Registers MAC TX, MAC RX