Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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6.10.3. IEEE 1588v2 Interface Clocks

Table 55.  Clock Signals for the IEEE 1588V2 Interfaces
Interface Signal Use legacy Ethernet 10G MAC Avalon® streaming interface Option Clock Signal

tx_egress_*

tx_etstamp_ins_*

On tx_156_25_clk
Off tx_312_5_clk

tx_time_of_day_*_10G_*

On tx_312_5_clk
Off

tx_time_of_day_*_1G_*

On gmii_tx_clk
Off

rx_ingress_*

On rx_156_25_clk
Off rx_312_5_clk

rx_time_of_day_*_10G_*

On rx_312_5_clk
Off

rx_time_of_day_*_1G_*

On gmii_rx_clk
Off