Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

6.7. Avalon® Streaming Flow Control Signals

Table 43.   Avalon® Streaming Flow Control Signals
Signal Operating Mode Direction Width Description
avalon_st_pause_data[] All In 2

This signal takes effect when the register bits, tx_pauseframe_enable[2:1], are both set to the default value 0.

Set this signal to the following values to trigger the corresponding actions.
  • 0x0: Stops pause frame generation.
  • 0x1: Generates an XON pause frame.
  • 0x2: Generates an XOFF pause frame. The MAC IP core sets the pause quanta field in the pause frame to the value in the tx_pauseframe_quanta register.
  • 0x3: Reserved.
avalon_st_tx_pause_length_valid All In 1 This signal is present in the MAC TX only variation.

Assert this signal to request the MAC IP core to suspend data transmission. When you assert this signal, ensure that a valid pause quanta is available on the avalon_st_tx_pause_length_data bus.

avalon_st_tx_pause_length_data[] All In 16 This signal is present in the MAC TX only variation.

Use this bus to specify the pause quanta in unit of quanta, where 1 unit = 512 bits time.

avalon_st_tx_pfc_gen_data[] 10G In n

(4–16)

n = 2 x Number of PFC queues parameter.

Each pair of bits is associated with a priority queue. Bits 0 and 1 are for priority queue 0, bits 2 and 3 are for priority queue 1, and so forth. Set the respective pair of bits to the following values to trigger the specified actions for the corresponding priority queue.

  • 0x0: Stops pause frame generation for the corresponding queue.
  • 0x1: Generates an XON pause frame for the corresponding queue.
  • 0x2: Generates an XOFF pause frame for the corresponding queue. The MAC IP core sets the pause quanta field in the pause frame to the value in the tx_pauseframe_quanta register.
  • 0x3: Reserved.
avalon_st_rx_pfc_pause_data[] 10G Out n

(2–8)

n = Number of PFC queues parameter.

When the MAC RX receives a pause frame, it asserts bit n of this signal when the pause quanta for the n th queue is valid (Pause Quanta Enable [n] = 1) and greater than 0. For each quanta unit, the MAC RX asserts bit n for eight clock cycle.

The MAC RX deasserts bit n of this signal when the pause quanta for the n th queue is valid (Pause Quanta Enable [n] = 1) and equal to 0. The MAC RX also deasserts bit n when the timer expires.

avalon_st_rx_pause_length_valid All Out 1 This signal is present in the MAC RX only variation.

The MAC IP core asserts this signal to request its link partner to suspend data transmission. When asserted, a valid pause quanta is available on the avalon_st_rx_pause_length_data bus.

avalon_st_rx_pause_length_data[] All Out 16 This signal is present only in the MAC RX only variation.

Specifies the pause quanta in unit of quanta, where 1 unit = 512 bits time.

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