Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface

Follow these steps to implement 32-bit to 64-bit adapters on the Avalon® streaming interface and XGMII, and uses the same register offsets to maintain backward compatibility with the legacy 10-Gbps Ethernet (10GbE) MAC IP core.
  1. Instantiate the LL Ethernet 10G MAC Intel® FPGA IP core in your design. To maintain compatibility on the interfaces, turn on the Use legacy Ethernet 10G MAC XGMII Interface, Use legacy Ethernet 10G MAC Avalon® memory-mapped interface , and Use legacy Ethernet 10G MAC Avalon® streaming interface options.
  2. Ensure that tx_312_5_clk and rx_312_5_clk are connected to 312.5 MHz clock sources. Intel recommends that you use the same clock source for these clock signals.
  3. Add a 156.25 MHz clock source for tx_156_25_clk and rx_156_25_clk. This 156.25 MHz clock source must be rise-to-rise synchronous to the 312.5 MHz clock source.
  4. Ensure that csr_clk is within 125 MHz to 156.25 MHz. Otherwise, some statistic counters may not be accurate.

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