Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

4.4.8. TX Timing Diagrams

Figure 14. Normal FrameThe following diagram shows the transmission of a normal frame.


Figure 15. Normal Frame with Preamble Passthrough Mode, Padding Bytes Insertion, and Source Address Insertion EnabledThe following diagram shows the transmission of good frames with preamble passthrough mode, padding bytes insertion, and source address insertion enabled.


Figure 16. Back-to-back Transmission of Normal Frames with Source Address Insertion Enabled.The following diagram shows back-to-back transmission of normal frames with source address insertion enabled. The MAC primary address registers are set to 0x000022334455.


Figure 17. Back-to-back Transmission of Normal Frames with Preamble Passthrough Mode EnabledThe following diagram shows back-to-back transmission of normal frames with preamble passthrough mode enabled.


Figure 18. Error Condition—UnderflowThe following diagrams show an underflow on the transmit datapath followed by the transmission of a normal frame.


An underflow happens in the middle of a frame that results in a premature termination on the XGMII. The remaining data from the Avalon® streaming transmit interface is still received after the underflow but the data is dropped. The transmission of the next frame is not affected by the underflow.

Figure 19. Error Condition—Underflow, continued


Figure 20. Short Frame with Padding Bytes Insertion EnabledThe following diagram shows the transmission of a short frame with no payload data. Padding bytes insertion is enabled.


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