Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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6.9.5. MII TX Signals

The signals below are present in the 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G operating modes.
Note: For 10M/100M/1G/2.5G and 10M/100M/1G/2.5G/10G variants, only tx_clkena signal is available.
Table 50.  MII TX Signals
Signal Direction Width Description
tx_clkena In 1 Clock enable from the PHY IP. This clock effectively divides gmii_tx_clk to 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.

For 10M/100M/1G/2.5G/10G and 10M/100M/1G/2.5G variants, this clock effectively divides gmii16b_tx_clk to 6.25 Mhz for 100 Mbps and 0.625 MHz for 10 Mbps.

tx_clkena_half_rate In 1 Clock enable from the PHY IP. This clock effectively divides gmii_tx_clk to 12.5 MHz for 100 Mbps and 1.25 MHz for 10 Mbps.
mii_tx_d[] Out 4 TX data bus.
mii_tx_en Out 1 When asserted, indicates the TX data is valid.
mii_tx_err Out 1 When asserted, indicates the TX data contains error.