Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

6.10.2. IEEE 1588v2 Ingress RX Signals

The signals below are present when you select the Enable time stamping option. This feature is available in the following operating modes: 10G, 1G/10G, 10M/100M/1G/10G, and 1G/2.5G, 1G/2.5G/10G ( Intel® Stratix® 10 devices only), and 10M/100M/1G/2.5G/5G/10G (USXGMII) ( Intel® Stratix® 10 devices only).

Table 54.  IEEE 1588v2 Ingress RX Signals
Signal Direction Width Description
rx_ingress_timestamp_96b_valid Out 1 When asserted, this signal qualifies the timestamp on rx_ingress_timestamp_96b_data[]. The MAC IP core asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket.
rx_ingress_timestamp_96b_data[] Out 96 Carries the 96-bit ingress timestamp in the following format:
  • Bits 48 to 95: 48-bit seconds field
  • Bits 16 to 47: 32-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field
The 96-bit timestamp is usually for noting the complete ToD and is useful in ordinary clock and boundary clock devices. The transparent clock typically uses 64-bit timestamp.
rx_ingress_timestamp_64b_valid Out 1 When asserted, this signal qualifies the timestamp on rx_ingress_timestamp_64b_data[]. The MAC IP core asserts this signal in the same clock cycle it asserts avalon_st_rx_startofpacket.
rx_ingress_timestamp_64b_data[] Out 64 Carries the 64-bit ingress timestamp in the following format:
  • Bits 16 to 63: 48-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field
This timestamp is used in transparent clock devices.
rx_time_of_day_96b_10g_data

(for 10G speed and 10M/100M/1G/2.5G/5G/10G (USXGMII) speed mode)

In 96 Carries the time of day (ToD) from an external ToD module to the MAC IP core in the following format:
  • Bits 48 to 95: 48-bit seconds field
  • Bits 16 to 47: 32-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field
rx_time_of_day_96b_1g_data

(for 10M, 100M, 1G, and 2.5G speeds)

rx_time_of_day_64b_10g_data

(for 10G speed and 10M/100M/1G/2.5G/5G/10G (USXGMII) speed mode)

In 64 Carries the ToD from an external ToD module the MAC IP core in the following format:
  • Bits 16 to 63: 48-bit nanoseconds field
  • Bits 0 to 15: 16-bit fractional nanoseconds field
rx_time_of_day_64b_1g_data

(for 10M, 100M, 1G, and 2.5G speeds)

rx_path_delay_10g_data

(for 10G speed and 10M/100M/1G/2.5G/5G/10G (USXGMII) speed mode)

In 16 or 24 Connect this bus to the PHY Intel® FPGA IP. This bus carries the path delay (residence time), measured between the physical network and the PHY side of the MAC IP Core (XGMII, GMII, or MII). The MAC IP core uses this value when generating the ingress timestamp to account for the delay. The path delay is in the following format:
  • Bits 0 to 9: Fractional number of clock cycle
  • Bits 10 to 15/21/23: Number of clock cycle
rx_path_delay_1g_data

(for 10M, 100M, 1G, and 2.5G speeds)

22
rx_ingress_p2p_val[] Out 46 Represents <meanPathDelay> for the current ingress port, which is used for peer-to-peer operations.
  • Bits 16 to 45: Link delay in nanoseconds field
  • Bits 0 to 15: Link delay in fractional nanoseconds field
rx_ingress_p2p_val_valid Out 1 When asserted, this signal indicates the rx_ingress_p2p_val is valid.

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