Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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Document Table of Contents

1. About LL Ethernet 10G MAC

Updated for:
Intel® Quartus® Prime Design Suite 18.1
IP Version 18.1

The Low Latency (LL) Ethernet 10G (10GbE) Media Access Controller (MAC) Intel® FPGA IP core is a configurable component that implements the IEEE 802.3-2008 specification. To build a complete Ethernet subsystem in an Intel FPGA device and connect it to an external device, you can use the LL 10GbE Intel® FPGA IP core with an Intel FPGA PHY IP core or any of the supported PHYs.

The figure below shows a system with the LL 10GbE MAC Intel® FPGA IP core.

Figure 1. Typical Application of LL 10GbE MAC

Note: Intel FPGAs implement and support the LL 10GbE Media Access Control (MAC) and Multi-Rate Ethernet PHY (PCS + PMA) IP to interface in a chip-to-chip or chip-to-module channel with external MGBASE-T and NBASE-T (1G/2.5G/5G/10Gb Ethernet) PHY standard devices. However, Intel FPGAs do not comply with or support these interface specifications to directly interface with the required twisted-pair copper cables such as CAT-5/6/7.