Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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Document Table of Contents
Document Table of Contents
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC
1.1. Features 1.2. Release Information 1.3. LL Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the LL Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Cyclone® 10 GX Devices
4. Functional Description
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers
5.9.1. Calculating Timing Adjustments
6. Interface Signals
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

1.4. Device Family Support

Table 4.   Intel® FPGA IP Core Device Support Levels
Device Support Level Definition
Preliminary Intel verifies the IP core with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. This IP core can be used in production designs with caution.
Final Intel verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. This IP core is ready to be used in production designs.

The IP core provides the following support for Intel FPGA device families.

Table 5.  Device Family Support for LL 10GbE MAC
Device Family Support Minimum Speed Grade
With 1588 Feature Without 1588 Feature
Intel® Stratix® 10 Preliminary -I2, -E2 -I3, -E3
Intel® Arria® 10 Final -I2, -E2 -I3, -E3
Intel® Cyclone® 10 GX Final -I5, -E5 -I6, -E6
Stratix® V Final -I3, -C3 -I4, -C4
Arria® V Final -I3, -C3 -I4, -C4

The following table lists possible LL 10GbE MAC and PHY configurations and the devices each configuration supports:

Table 6.  Device Family Support for LL 10GbE MAC and PHY Configurations
LL 10GbE MAC Mode PHY Arria® V Intel® Arria® 10 Intel® Cyclone® 10 GX Stratix® V Intel® Stratix® 10
10G 10GBASE-R Arria® V GZ — — Yes —
10GBASE-R with IEEE 1588v2 feature Arria® V GZ — — Yes —
  • 10GBASE-R
  • 10GBASE-R Low Latency
  • 10GBASE-R Register Mode
  • 10GBASE-R with KR-FEC
 — Yes Yes —  
  • 10GBASE-R
  • 10GBASE-R Low Latency
  • 10GBASE-R with IEEE 1588v2 feature
  • 10GBASE-R with KR-FEC
 — — — — Yes
1G/2.5G/10G 1G/2.5G/10G (MGBASE-T) Multi-rate 2 — Yes Yes — Yes
1G/2.5G/10G (MGBASE-T) Multi-rate with IEEE 1588v2 feature — — — — Yes
10M/100M/1G/2.5G/5G/10G (USXGMII) 10M/100M/1G/2.5G/5G/10G (USXGMII) Multi-rate 3 — Yes Yes — Yes
10M/100M/1G/2.5G/5G/10G (USXGMII) Multi-rate with IEEE 1588v2 feature — — — — Yes
1G/2.5G 1G/2.5G Multi-rate Arria® V GX/GT/SX/ST Yes Yes — Yes
1G/2.5G Multi-rate with IEEE 1588v2 feature Arria® V GX/GT/SX/ST Yes Yes — Yes
2.5G Multi-rate Arria® V GX/GT/SX/ST Yes — — Yes
1G/2.5G with IEEE 1588v2 feature 2.5G Multi-rate with IEEE 1588v2 feature Arria® V GX/GT/SX/ST Yes — — Yes
10M/100M/1G/10G — Arria® V GZ Yes Yes Yes Yes
10M/100M/1G/10G MAC with IEEE 1588v2 feature — Arria® V GZ Yes Yes Yes Yes
10M/100M/1G/10G 1G/10GbE Arria® V GZ Yes Yes Yes —
10G Backplane Ethernet 10GBASE-KR — — — — Yes
1G/10G 1G/10GbE Yes Yes Yes Yes —
1G/10G with IEEE 1588v2 feature 1G/10GbE with IEEE 1588v2 feature Yes Yes Yes Yes —
10M/100M/1G/10G MAC with IEEE 1588v2 feature 1G/10GbE Arria® V GZ Yes Yes Yes —
10M/100M/1G/2.5G 1G/2.5G Multi-rate with SGMII bridge enabled — — — — Yes
10M/100M/1G/2.5G/10G 1G/2.5G/10G (MGBASE-T) Multi-rate with SGMII bridge enabled — — — — Yes
Related Information
2 Connected to an external MGBASE-T PHY.
3 Connected to an external NBASE-T PHY.
Level Two Title