Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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6.9.6. MII RX Signals

The signals below are present in the 10M/100M/1G/10G, 10M/100M/1G/2.5G, and 10M/100M/1G/2.5G/10G operating modes.
Note: For 10M/100M/1G/2.5G and 10M/100M/1G/2.5G/10G variants, only rx_clkena signal is available.
Table 51.  MII RX Signals
Signal Direction Width Description
rx_clkena In 1 Clock enable from the PHY IP for 100 Mbps and 10 Mbps operations. This clock effectively divides gmii_rx_clk to 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.

For 10M/100M/1G/2.5G/10G and 10M/100M/1G/2.5G variants, this clock effectively divides gmii16b_rx_clk to 6.25 Mhz for 100 Mbps and 0.625 MHz for 10 Mbps.

rx_clkena_half_rate In 1 Clock enable from the PHY IP for 100 Mbps and 10 Mbps operations. This clock effectively runs at half the rate of rx_clkena and divides gmii_rx_clk to 12.5 MHz for 100 Mbps and 1.25 MHz for 10 Mbps. The rising edges of this signal and rx_clkena must align.
mii_rx_d[] In 4 RX data bus.
mii_rx_dv In 1 When asserted, indicates the RX data is valid.
mii_rx_err In 1 When asserted, indicates the RX data contains error.