Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

Download PDF
ID 683426
Date 11/17/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About LL Ethernet 10G MAC 2. Getting Started 3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples 4. Functional Description 5. Configuration Registers 6. Interface Signals 7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives 8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide
1. About LL Ethernet 10G MAC x
1.1. Features 1.2. Release Information 1.3. LL Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.1. Features x
1.1.1. LL Ethernet 10G MAC and Legacy 10-Gbps Ethernet MAC
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 2.4. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 2.5. Files Generated for Intel IP Cores (Legacy Parameter Editor) 2.6. Simulating Intel® FPGA IP Cores 2.7. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.8. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.9. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.10. Design Considerations for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC 2.10.2. Timing Constraints 2.10.3. Jitter on PLL Clocks
2.10.1. Migrating from Legacy Ethernet 10G MAC to LL Ethernet 10G MAC x
2.10.1.1. Migration—32-bit Datapath on Avalon® Streaming Interface 2.10.1.2. Migration—Maintains 64-bit on Avalon® Streaming Interface
2.10.2. Timing Constraints x
2.10.2.1. Pseudo-Static CSR Fields 2.10.2.2. Clock Crosser 2.10.2.3. Dual Clock FIFO
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples x
3.1. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Stratix® 10 Devices 3.2. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Arria® 10 Devices 3.3. LL Ethernet 10G MAC Intel® FPGA IP Design Example for Intel® Cyclone® 10 GX Devices
4. Functional Description x
4.1. Architecture 4.2. Interfaces 4.3. Frame Types 4.4. TX Datapath 4.5. RX Datapath 4.6. Flow Control 4.7. Reset Requirements 4.8. Supported PHYs 4.9. XGMII Error Handling (Link Fault) 4.10. IEEE 1588v2
4.4. TX Datapath x
4.4.1. Padding Bytes Insertion 4.4.2. Address Insertion 4.4.3. CRC-32 Insertion 4.4.4. XGMII Encapsulation 4.4.5. Inter-Packet Gap Generation and Insertion 4.4.6. XGMII Transmission 4.4.7. Unidirectional Feature 4.4.8. TX Timing Diagrams
4.5. RX Datapath x
4.5.1. XGMII Decapsulation 4.5.2. CRC Checking 4.5.3. Address Checking 4.5.4. Frame Type Checking 4.5.5. Length Checking 4.5.6. CRC and Padding Bytes Removal 4.5.7. Overflow Handling 4.5.8. RX Timing Diagrams
4.5.5. Length Checking x
4.5.5.1. Frame Length 4.5.5.2. Payload Length
4.6. Flow Control x
4.6.1. IEEE 802.3 Flow Control 4.6.2. Priority-Based Flow Control
4.6.1. IEEE 802.3 Flow Control x
4.6.1.1. Pause Frame Reception 4.6.1.2. Pause Frame Transmission
4.6.2. Priority-Based Flow Control x
4.6.2.1. PFC Frame Reception 4.6.2.2. PFC Frame Transmission
4.8. Supported PHYs x
4.8.1. 10GBASE-R Register Mode
4.10. IEEE 1588v2 x
4.10.1. Architecture 4.10.2. TX Datapath 4.10.3. RX Datapath 4.10.4. Frame Format
4.10.4. Frame Format x
4.10.4.1. PTP Packet in IEEE 802.3 4.10.4.2. PTP Packet over UDP/IPv4 4.10.4.3. PTP Packet over UDP/IPv6
5. Configuration Registers x
5.1. Register Map 5.2. Register Access Definition 5.3. Primary MAC Address 5.4. MAC Reset Control Register 5.5. TX Configuration and Status Registers 5.6. Flow Control Registers 5.7. Unidirectional Control Registers 5.8. RX Configuration and Status Registers 5.9. Timestamp Registers 5.10. ECC Registers 5.11. Statistics Registers
5.1. Register Map x
5.1.1. Mapping 10-Gbps Ethernet MAC Registers to LL Ethernet 10G MAC Registers
5.9. Timestamp Registers x
5.9.1. Calculating Timing Adjustments
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Speed Selection Signal 6.3. Error Correction Signals 6.4. Unidirectional Signals 6.5. Avalon® Memory-Mapped Interface Programming Signals 6.6. Avalon® Streaming Data Interfaces 6.7. Avalon® Streaming Flow Control Signals 6.8. Avalon® Streaming Status Interface 6.9. PHY-side Interfaces 6.10. IEEE 1588v2 Interfaces
6.6. Avalon® Streaming Data Interfaces x
6.6.1. Avalon® Streaming TX Data Interface Signals 6.6.2. Avalon® Streaming RX Data Interface Signals 6.6.3. Avalon® Streaming Data Interface Clocks
6.8. Avalon® Streaming Status Interface x
6.8.1. Avalon® Streaming Interface TX Status Signals 6.8.2. Avalon® Streaming Interface RX Status Signals
6.9. PHY-side Interfaces x
6.9.1. XGMII TX Signals 6.9.2. XGMII RX Signals 6.9.3. GMII TX Signals 6.9.4. GMII RX Signals 6.9.5. MII TX Signals 6.9.6. MII RX Signals
6.10. IEEE 1588v2 Interfaces x
6.10.1. IEEE 1588v2 Egress TX Signals 6.10.2. IEEE 1588v2 Ingress RX Signals 6.10.3. IEEE 1588v2 Interface Clocks
1. About LL Ethernet 10G MAC
2. Getting Started
3. LL Ethernet 10G MAC Intel® FPGA IP Design Examples
4. Functional Description
5. Configuration Registers
6. Interface Signals
7. Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide Archives
8. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

5.9.1. Calculating Timing Adjustments

You can derive the required timing adjustments in ns and fns from the hardware PMA delay.

Table 32.  Hardware PMA Delay
Type Device PMA Mode (bit) Latency MAC Configurations
TX RX
Digital12

Arria® V GZ

Stratix® V

40 123 UI 87 UI

10GbE

10G of 10M-10GbE
32 99 UI 84 UI 10GbE
10 53 UI 26 UI 1G/100M/10M of 10M-10GbE

Arria® V GX/GT/SX/ST

10 42 UI 44 UI 1G/2.5GbE

Intel® Arria® 10

40 147 UI 66.5 UI

10GbE

10G of 10M-10GbE
32 123 UI 58.5 UI

10GbE

10G of 10M-10GbE
10 43 UI 24.5 UI

1G/100M/10M of 10M-10GbE

1G/2.5GbE
Intel® Cyclone® 10 GX 40 147 UI 66.5 UI

10GbE

10G of 10M-10GbE
32 123 UI 58.5 UI

10GbE

10G of 10M-10GbE
10 43 UI 24.5 UI

1G/100M/10M of 10M-10GbE

1G/2.5GbE

Intel® Stratix® 10

40 127 UI 48.5 UI

10GbE

10G of 10M-10GbE
32 107 UI 44.5 UI

10GbE

10G of 10M-10GbE
10 43 UI 26.5 UI

1G/100M/10M of 10M-10GbE

1G/2.5GbE
Analog13

Arria® V

Stratix® V

— -1.1 ns 1.75 ns All

Arria® V GX/GT/SX/ST

Intel® Arria® 10

Intel® Cyclone® 10 GX

Intel® Stratix® 10

— 0.69 ns 3.54 ns

10G of 1G/2.5G/10Gbe
0.18 ns 3.03 ns

1G/2.5GbE

The example below shows the required calculation for a 10M – 10GbE design targeting a Stratix® V device.

Table 33.  Example: Calculating RX Timing Adjustments for 10M – 10GbE Design in a Stratix® V Device
Step Description 10G 10M, 100M or 1G
1 Identify the digital latency for the device. For Stratix® V using the PMA mode of 40 bits, the digital latency is 87 UI. For Stratix® V using the PMA mode of 10 bits, the digital latency is 26 UI.
2 Convert the digital latency in UI to ns. 87 UI * 0.097 = 8.439 ns 26 UI * 0.8 = 20.8 ns
3 Add the analog latency to the digital latency in ns. 8.439 ns + 1.75 ns = 10.189 ns 20.8 ns + 1.75 ns = 22.55 ns
4 Add any external PHY delay to the total obtained in step 3. In this example, an external PHY delay of 1 ns is assumed. 10.189 ns + 1 ns = 11.189 ns 22.55 ns + 1 ns = 23.55 ns
5 Convert the total latency to ns and fns in hexadecimal.

ns: 0xB

fns: 0.189 * 65536 = 0x3062

ns: 0x17

fns: 0.55 * 65536 = 0x8CCC
6 Configure the respective registers.

rx_ns_adjustment_10G = 0xB

rx_fns_adjustment_10G = 0x3062

rx_ns_adjustment_mult_speed = 0x17

rx_fns_adjustment_mult_speed = 0x8CCC

Related Information
12 For 10G, 1 UI is 97 ps. For 2.5G, 1 UI is 320 ps. For 10M/100M/1G,1 UI is 800 ps.
13 Valid for the HSSI clock routing using periphery clock. Other clocking scheme might result in deviation of a few ns.
Level Two Title