Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

5.9.1. Calculating Timing Adjustments

You can derive the required timing adjustments in ns and fns from the hardware PMA delay.

Table 31.  Hardware PMA Delay
Type Device PMA Mode (bit) Latency MAC Configurations
TX RX
Digital12

Arria® V GZ

Stratix® V

40 123 UI 87 UI

10GbE

10G of 10M-10GbE

32 99 UI 84 UI 10GbE
10 53 UI 26 UI 1G/100M/10M of 10M-10GbE

Arria® V GX/GT/SX/ST

10 42 UI 44 UI 1G/2.5GbE

Intel® Arria® 10

40 147 UI 66.5 UI

10GbE

10G of 10M-10GbE

32 123 UI 58.5 UI

10GbE

10G of 10M-10GbE

10 43 UI 24.5 UI

1G/100M/10M of 10M-10GbE

1G/2.5GbE

Intel® Cyclone® 10 GX 40 147 UI 66.5 UI

10GbE

10G of 10M-10GbE

32 123 UI 58.5 UI

10GbE

10G of 10M-10GbE

10 43 UI 24.5 UI

1G/100M/10M of 10M-10GbE

1G/2.5GbE

Intel® Stratix® 10

40 127 UI 48.5 UI

10GbE

10G of 10M-10GbE

32 107 UI 44.5 UI

10GbE

10G of 10M-10GbE

10 43 UI 26.5 UI

1G/100M/10M of 10M-10GbE

1G/2.5GbE

Analog13

Arria® V

Stratix® V

-1.1 ns 1.75 ns All

Arria® V GX/GT/SX/ST

Intel® Arria® 10

Intel® Cyclone® 10 GX

Intel® Stratix® 10

0.69 ns 3.54 ns

10G of 1G/2.5G/10Gbe

0.18 ns 3.03 ns

1G/2.5GbE

The example below shows the required calculation for a 10M – 10GbE design targeting a Stratix® V device.

Table 32.  Example: Calculating RX Timing Adjustments for 10M – 10GbE Design in a Stratix® V Device
Step Description 10G 10M, 100M or 1G
1 Identify the digital latency for the device. For Stratix® V using the PMA mode of 40 bits, the digital latency is 87 UI. For Stratix® V using the PMA mode of 10 bits, the digital latency is 26 UI.
2 Convert the digital latency in UI to ns. 87 UI * 0.097 = 8.439 ns 26 UI * 0.8 = 20.8 ns
3 Add the analog latency to the digital latency in ns. 8.439 ns + 1.75 ns = 10.189 ns 20.8 ns + 1.75 ns = 22.55 ns
4 Add any external PHY delay to the total obtained in step 3. In this example, an external PHY delay of 1 ns is assumed. 10.189 ns + 1 ns = 11.189 ns 22.55 ns + 1 ns = 23.55 ns
5 Convert the total latency to ns and fns in hexadecimal.

ns: 0xB

fns: 0.189 * 65536 = 0x3062

ns: 0x17

fns: 0.55 * 65536 = 0x8CCC

6 Configure the respective registers.

rx_ns_adjustment_10G = 0xB

rx_fns_adjustment_10G = 0x3062

rx_ns_adjustment_mult_speed = 0x17

rx_fns_adjustment_mult_speed = 0x8CCC

12 For 10G, 1 UI is 97 ps. For 2.5G, 1 UI is 320 ps. For 10M/100M/1G,1 UI is 800 ps.
13 Valid for the HSSI clock routing using periphery clock. Other clocking scheme might result in deviation of a few ns.

Did you find the information on this page useful?

Characters remaining:

Feedback Message