Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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5.10. ECC Registers

The ECC registers are used when you turn on Enable ECC on memory blocks. They are reserved when not used.

Table 33.  ECC Registers
Word Offset Register Name Description Access HW Reset Value

0x0240

0x0820

ecc_status
  • Bit 0—a value of '1' indicates that an ECC error was detected and corrected. The user application must write 1 to this bit to clear it.
  • Bit 1—a value of '1' indicates that an ECC error was detected but not corrected. The user application must write 1 to this bit to clear it.
  • Bits 31:2—reserved.

If you turn on Use legacy Ethernet 10G MAC Avalon® memory-mapped interface , the word offset is 0x0820. Otherwise, the word offset is 0x0240.

RWC 0x0

0x0241

0x0821

ecc_enable
  • Bit 0—specifies how detected and corrected ECC errors are reported.

    0: Reported by the ecc_status[0] register bit only.

    1: Reported by the ecc_status[0] register bit and the ecc_err_det_corr signal.

  • Bit 1—specifies how detected and uncorrected ECC errors are reported.

    0: Reported by the ecc_status[0] register bit only.

    1: Reported by the ecc_status[0] register bit and the ecc_err_det_uncorr signal.

  • Bits 31:2—reserved.

If you turn on Use legacy Ethernet 10G MAC Avalon® memory-mapped interface , the word offset is 0x0821. Otherwise, the word offset is 0x0241.

RW 0x0