Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Document Table of Contents

6.5. Avalon® Memory-Mapped Interface Programming Signals

Table 39.   Avalon® Memory-Mapped Interface Programming Signals
Signal Direction Width Description
csr_address[] In 10/2 Use this bus to specify the register address to read from or write to.

The width is 13 bits when you enable the Use Legacy Ethernet 10G MAC Avalon® memory-mapped interface option.

csr_read In 1 Assert this signal to request a read.
csr_readdata[] Out 32 Data read from the specified register. The data is valid when thecsr_waitrequest signal is deasserted.
csr_write In 1 Assert this signal to request a write.
csr_writedata[] In 32 Data to be written to the specified register. The data is written when the csr_waitrequest signal is deasserted.
csr_waitrequest Out 1

When asserted, this signal indicates that the MAC IP core is busy and not ready to accept any read or write requests.

  • When you have requested for a read or write, keep the control signals to the Avalon® memory-mapped interface constant while this signal is asserted. The request is complete when it is deasserted.
  • This signal can be high or low during idle cycles and reset. Therefore, the user application must not make any assumption of its assertion state during these periods.

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