Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
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5.4. MAC Reset Control Register

This register is used only in 10G, 1G/10G, and 10M/100M/1G/10G operating modes.

Table 24.  MAC Reset Control Register
Word Offset Register Name Description Access HW Reset Value

0x001F

0x08FF

mac_reset_control

The user application can use the specified bits in this register to reset the MAC datapaths. The effect is the same as asserting the tx_rst_n or rx_rst_n signals.

  • Bit 0—TX datapath reset.

    0: Stops the reset process.

    1: Starts the reset process.

  • Bits 7:1—reserved.
  • Bit 8—RX datapath reset.

    0: Stops the reset process.

    1: Starts the reset process.

  • Bits 31:9—reserved.

If you turn on Use legacy Ethernet 10G MAC Avalon® memory-mapped interface , the word offset is 0x08FF. Otherwise, the word offset is 0x001F.

RW 0x0