|Avalon® streaming interface||
The client-side interface of the MAC employs the Avalon® streaming protocol, which is a synchronous point-to-point, unidirectional interface that connects the producer of a data stream (source) to a consumer of the data (sink). The key properties of this interface include:
In the MAC IP core, the Avalon® streaming interface acts as a sink in the TX datapath and source in the RX datapath. This interface supports packets, backpressure, and error detection. It operates at either 312.5 MHz or 156.25 MHz depending on the operating mode. The ready latency on this interface is 0.
|Avalon® memory-mapped Control and Status Register Interface||The Avalon® memory-mapped control and status register interface is an Avalon® memory-mapped slave port. This interface uses word addressing which provides access to the configuration and status registers, and statistics counters.|
|XGMII||In 10G mode, the network-side interface of the MAC IP core implements the XGMII protocol. Depending on the configuration, the XGMII consists of 32- or 64-bit data bus and 4- or 8-bit control bus operating at 312.5 MHz. This interface operates at 322.265625 MHz if the 10GBASE-R register mode is enabled. The data bus carries the MAC frame with the most significant byte occupying the least significant lane.|
In 1G/10G and 10M/100M/1G/10G operating modes, the network-side interface of the MAC IP core implements 8 bits wide GMII protocol when the MAC operates at 1 Gbps. This 8-bit interface supports gigabit operations at 125 MHz.
In 1G/2.5G operating mode, the network-side interface of the MAC IP core implements 16 bits wide GMII protocol. This 16-bit interface supports 2.5G operations at 156.25 MHz and 1G operations at 62.5 MHz.
For 10M/100M/1G/2.5G and 10M/100M/1G/2.5G/10G variants, the 10M/100M operating mode uses 16 bits wide GMII protocol with TX /RX clock enabled to downsample the data rate /10 and /100. No MII interfaces are available.
|MII||In 10M or 100M mode, the network-side interface of the MAC IP core implements the MII protocol. This 4-bit MII supports 10-Mbps and 100-Mbps operations at 125 MHz, with a clock enable signal that divides the clock to effective rates of 2.5 MHz for 10 Mbps and 25 MHz for 100 Mbps.|
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