Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide

ID 683426
Date 3/01/2022
Public
Download
Document Table of Contents

6.8.1. Avalon® Streaming Interface TX Status Signals

Table 44.   Avalon® Streaming Interface TX Status Signals
Signal Direction Width Description
avalon_st_txstatus_valid Out 1

When asserted, this signal qualifies the avalon_st_txstatus_data[] and avalon_st_txstatus_error[] signals.

avalon_st_txstatus_data[] Out 40

Contains information about the TX frame.

  • Bits 0 to 15: Payload length.
  • Bits 16 to 31: Packet length.
  • Bit 32: When set to 1, indicates a stacked VLAN frame. Ignore this bit when the MAC is configured not to detect stacked VLAN frames (tx_vlan_detection[0] = 1).
  • Bit 33: When set to 1, indicates a VLAN frame. Ignore this bit when the MAC is configured not to detect VLAN frames (tx_vlan_detection[0] = 1).
  • Bit 34: When set to 1, indicates a control frame.
  • Bit 35: When set to 1, indicates a pause frame.
  • Bit 36: When set to 1, indicates a broadcast frame.
  • Bit 37: When set to 1, indicates a multicast frame.
  • Bit 38: When set to 1, indicates a unicast frame.
  • Bit 39: When set to 1, indicates a PFC frame.

This status signal is valid only if the TX frame is valid. For example, bit 35 is not asserted if a pause frame is oversized.

avalon_st_txstatus_error[] Out 7

When set to 1, the respective bit indicates the following error type in the TX frame:

  • Bit 0: Undersized frame.
  • Bit 1: Oversized frame.
  • Bit 2: Payload length error.
  • Bit 3: Unused.
  • Bit 4: Underflow.
  • Bit 5: The avalon_st_tx_error input signal from client is asserted.
  • Bit 6: Unused.

The error status is invalid when an overflow occurs.

avalon_st_tx_pfc_status_valid Out 1

When asserted, this signal qualifies the avalon_st_tx_pfc_status_data[] signal. This signal applies only to 10G operating mode.

avalon_st_tx_pfc_status_data[] Out n

(4 - 16)

n = 2 × Number of PFC queues parameter.

When set to 1, the respective bit indicates the flow control request to the remote partner, for example:

  • Bit 0: XON request for priority queue 0
  • Bit 1: XOFF request for priority queue 0
  • Bit 2: XON request for priority queue 1
  • Bit 3: XOFF request for priority queue 1
  • Bit 4: XON request for priority queue 2
  • Bit 5: XOFF request for priority queue 2

When a pair of bits (Example: Bit 0 and Bit 1, Bit 3 and Bit 4, etc.) is set to 0, the respective bit indicates there is no flow control frame sent.

This signal applies only to the 10G operating mode.

Did you find the information on this page useful?

Characters remaining:

Feedback Message